Space radiation and FPGA for space applications - GENERA Technologies

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Space radiation and FPGA for space applications

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FPGA development for space applications_
Radiation and high energy particles
Unlike most applications on the Earth's surface, space applications are subject to high ionizing radiation. This radiation is emitted by high-energy particles, and is the cause of errors in electronic systems. Depending on the origin of the particles, the radiation to be considered can be divided into three types:

    • Radiation trapped in the magnetosphere (Van Allen radiation belts): particles from the sun, trapped in the Earth's magnetic field. Due to the asymmetry of the Earth's magnetic field, the radiation from the belts is unevenly distributed. Its density is influenced by solar flames, increasing greatly in case of solar storms.
    • Cosmic radiation: galactic cosmic rays from outside the solar system, have one of their origins in supernova explosions.
    • Solar radiation: solar energetic particles from the sun's magnetic field.
Space radiation. Source: nasa.gov
Effects of radiation on FPGAs. Types of errors
All silicon chips are susceptible to the effects of radiation, both ionizing and non-ionizing. Electron-hole pairs are created in MOS structures, so the leakage current increases and the threshold voltage of the transistor varies. They can be classified into two large groups: cumulative effects and singular effects.

    • Cumulative: the Total Ionizing Dose (TID) is produced by the gradual increase in trapped charges and defects that are generated by ionization processes during radiation exposure, and which accumulate mainly in the dielectric layers of the devices. For the specific case of MOS transistors, the TID causes variations in the threshold voltage and a decrease in mobility in the conduction channel, together with an increase in the leakage current between drain and source in the cut-off region of the transistor. This effect does not produce immediate errors, but a prolonged exposure - due to its cumulative effect - ages and damages the electronic device, thus limiting its useful life.

    • Singular Effects (Single Event Effects, SEEs): they are caused by a single ionizing particle that, when passing through a certain sensitive region of the device, creates an induced charge that can immediately and temporarily affect its correct operation or even destroy the device. This article focuses solely on the singular SEE effects.

The SEEs are divided into permanent or destructive (hard errors) and reversible or non-destructive (soft errors), the latter are correctable by various techniques.

Permanent or destructive SEE (Single Event Effects) (hard errors):
    • SEGR (Single Event Gate Rupture) and SEB (Single Event Induced Burnout): both are produced by a high current induced by the radiation particle. In SEGR the result is the breakage of a logic gate, and in SEB a part of the circuit.
    • SEL (Single Event Induced Latchup): a parasitic structure similar to a silicon controlled rectifier (SCR) is created, allowing the circulation of high currents that can cause permanent damage. Depending on the case, it can cause instantaneous damage or cause damage over time. Defined as destructive but fixable by stopping powering the circuit if a marked current intensity limit is not exceeded.

SEE (Single Event Effects) reversible or non-destructive (soft errors):
    • SEU (Single Event Upsets): produced by a radiation particle that affects a memory data. A memory data bit reverses its logical value (from '0' to '1' or from '1' to '0') if the particle load exceeds the critical load of the device.
    • MBU (Multiple Bit Upsets): SEU that affects more than one memory data.
    • SET (Single Event Transient): produced by a high voltage induced by the radiation particle. It causes an error in the bit of a combinational circuit, propagating itself throughout the circuit. A SEU is considered in case of affecting the bit of a sequential circuit.
    • SEFI (Single Event Functional Interrupt): particular case of SEU that produces a variation in the basic or essential functionality of the device.

Generation and transport of charges by the effect of a SEE in the drain region of a NMOS transistor. Source: [3].
Different FPGA technologies. Relationship with regard SEEs and reconfigurability
The selection process of FPGAs for space applications takes into account two major factors: immunity to SEE and the versatility of the system (possibility of reconfiguration).

Depending on the technology used by the FPGA to carry out its configuration function, three types of FPGAs are distinguished:
    • Antifuse: they use Antifuse technology configuration cells developed by Actel (for its family of programmable logic). They are programmed once (one-time programmable, OTP), they maintain their value permanently and there is no going back once they are programmed. They are defined as non-volatile, which means that the FPGAs implemented using this technology are "instant on" and do not require external configuration sources.

    • Flash: They use Flash technology configuration cells that are automatically dumped into SRAM configuration cells upon power-on, startup and/or reboot. They are also "instant on", requiring no external configuration sources. They are non-volatile and re-programmable a limited number of times. Flash memory cells have a high immunity against SEE.

    • SRAM: use SRAM technology configuration cells for storage of configuration data. They are highly re-programmable, but volatile. Their cost is lower in relation to other types of FPGAs but they require an external non-volatile memory for their configuration after they are turned on or restarted. They are susceptible to SEEs, since they are based on volatile static RAM (in SRAM, a bit of data is stored using the state of a transistor memory cell, typically using MOSFETs).
FPGA types in function of configuration data storage technology
Type of FPGA
Antifuse
SRAM
Flash
Reconfigurable
No
Yes
Yes
Volatile
No
Yes
No
Immunity against SEE
Very high
Low
Medium-high
Cost
Very high
Medium
High
FPGAs based on Antifuse technology have been and are widely used in space applications due to their high immunity against SEEs. However, given their non-reconfigurability, more and more space applications use FPGAs based on other technologies. Space applications that use FPGAs based on Flash technology are more recent solutions to those based on antifuse technology, but with good results due to the relationship between their resistance to SEEs and their ability to reconfigure. These are usually systems whose manufacture implements an extra shield against radiation. FPGAs based on Antifuse and Flash require additional processes in addition to the CMOS process to create the rest of the chip, while FPGAs based on SRAM technology are manufactured using the same CMOS process as the rest of the chip, they have a reconfiguration capacity almost unlimited and higher performance, since they are usually a generation or two ahead of Flash and Anti-Fuse technologies, as well as a lower cost than those based on Flash and Anti-Fuse technologies. In return, these SRAM-based solutions must implement an external configuration system with a Flash or EEPROM type memory to store the files used in the FPGA reprogramming and have a higher power consumption.

The FPGA manufacturing process technology, which determines the size of the transistor structure, affects the degree of tolerance to radiation: FPGAs made with processes of 40nm or less, show an improvement in tolerance to radiation.

Selecting the best FPGA device for a specific task or set of tasks can be difficult because there are many families, each offering different resources, performances, tolerances, interfaces, and development tools.
Mitigation techniques for errors caused by the effects of radiation
The effects caused by radiation on SRAM-based FPGAs, due to their susceptibility to SEEs, meant that -for a time- such technology was considered unsuitable for aerospace and space applications. Currently, manufacturing processes (substrates layers, 20nm to 7nm FPGAs,...) and mitigation techniques are employed, with the result that SRAM technology FPGAs are found in systems such as the Mars Curiosity Rover.

The following error mitigation techniques, or a set of them, are implemented in FPGA developments for space applications:

Hardware mitigation techniques for SEE:
    • Hardware shielding against radiation
    • Redundancy techniques

Mitigation software techniques for SEE:
    • Configuration Data Scrubbing
    • Error detection and correction codes and parity
    • Checkpointing and Rollback Recovery
    • Temporary redundancy
    • Specific coding of state machines
    • TMR - triple redundancy techniques
However, FPGA-based implementations and developments are not an easy task, and you may not always have the experience, resources, or time to fulfill your planning.
Our team of engineers specialized in FPGAs and SoC / MPSoC offers you experience and services to develop your product, with the mission of helping you reduce your development cycles. At GENERA Technologies we have a long history helping our clients to convert the signal acquired by the sensor into processed, reliabilted and real-time information in the shortest latency in a wide range of applications and sectors. Contac us.
References
[1] Radiation Impacts on Satellites due to GCRs and SEPs.
Mike Xapsos GSFC, Code 561, NASA.
https://ccmc.gsfc.nasa.gov/RoR_WWW/SWREDI/training-for-engineers/Xapsos_Space_Weather_Training_GSFC.pdf

[2] SEU Mitigation Techniques for Advanced Reprogrammable FPGA in Space.
Department of Computer Science and Engineering - CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden, FREDRIK BROSSER, EMIL MILH.
http://publications.lib.chalmers.se/records/fulltext/202966/202966.pdf

[3] DISEÑO CMOS DE SISTEMAS DE FRONT-END PARA INSTRUMENTACIÓN AMBIENTAL EN MARTE.
Dpto. de Electrónica y Electromagnetismo – Facultad de Física Instituto de Microelectrónica de Sevilla, UNIVERSIDAD DE SEVILLA – CSIC.
https://idus.us.es/handle/11441/52295

[4] FAULT MANAGEMENT TECHNIQUES FOR SYSTEMS WITH SRAM-BASED FPGAS.
Universidad Politécnica de Madrid - Escuela Técnica Superior de Ingenieros de Telecomunicación.
http://oa.upm.es/37901/1/IGNACIO_HERRERA_ALZU_01.pdf

[5] High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond. IEEE.
https://ieeexplore.ieee.org/document/7086415

[6] GENERA's own sources.

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